U.S. Pat. No. 10,729,980

DESCRIPTION OF EMBODIMENTS

For the purposes of explanation, numerous specific details are set forth to provide a thorough understanding of the various embodiments described below. However, it will be apparent to a skilled practitioner in the art that the embodiments may be practiced without some of these specific details. In other instances, well-known structures and devices are shown in block diagram form to avoid obscuring the underlying principles, and to provide a more thorough understanding of embodiments. Although some of the following embodiments are described with reference to a graphics processor, the techniques and teachings described herein may be applied to various types of circuits or semiconductor devices, including general purpose processing devices or graphic processing devices. Reference herein to “one embodiment” or “an embodiment” indicate that a particular feature, structure, or characteristic described in connection or association with the embodiment can be included in at least one of such embodiments. However, the appearances of the phrase “in one embodiment” in various places in the specification do not necessarily all refer to the same embodiment.

In the following description and claims, the terms “coupled” and “connected,” along with their derivatives, may be used. It should be understood that these terms are not intended as synonyms for each other. “Coupled” is used to indicate that two or more elements, which may or may not be in direct physical or electrical contact with each other, co-operate or interact with each other. “Connected” is used to indicate the establishment of communication between two or more elements that are coupled with each other.

In the description that follows,FIGS. 1-14provide an overview of exemplary data processing system and graphics processor logic that incorporates or relates to the various embodiments.FIGS. 15-25provide specific details of the various embodiments. Some aspects of the following embodiments are described with reference to a graphics processor, while other aspects are described with respect to a general-purpose processor, such as a central processing unit (CPU). Similar techniques and teachings can be applied to other types of circuits or semiconductor devices, including but not limited to a many integrated core processor, a GPU cluster, or one or more instances of a field programmable gate array (FPGA). In general, the teachings are applicable to any processor or machine that manipulates or processes image (e.g., sample, pixel), vertex data, or geometry data.

System Overview

FIG. 1is a block diagram of a processing system100, according to an embodiment. In various embodiments the system100includes one or more processors102and one or more graphics processors108, and may be a single processor desktop system, a multiprocessor workstation system, or a server system having a large number of processors102or processor cores107. In one embodiment, the system100is a processing platform incorporated within a system-on-a-chip (SoC) integrated circuit for use in mobile, handheld, or embedded devices.

In one embodiment the system100can include or be incorporated within a server-based gaming platform, a game console, including a game and media console, a mobile gaming console, a handheld game console, or an online game console. In some embodiments the system100is a mobile phone, smart phone, tablet computing device or mobile Internet device. The processing system100can also include, couple with, or be integrated within a wearable device, such as a smart watch wearable device, smart eyewear device, augmented reality device, or virtual reality device. In some embodiments, the processing system100is a television or set top box device having one or more processors102and a graphical interface generated by one or more graphics processors108.

In some embodiments, the one or more processors102each include one or more processor cores107to process instructions which, when executed, perform operations for system and user software. In some embodiments, each of the one or more processor cores107is configured to process a specific instruction set109. In some embodiments, instruction set109may facilitate Complex Instruction Set Computing (CISC), Reduced Instruction Set Computing (RISC), or computing via a Very Long Instruction Word (VLIW). Multiple processor cores107may each process a different instruction set109, which may include instructions to facilitate the emulation of other instruction sets. Processor core107may also include other processing devices, such a Digital Signal Processor (DSP).

In some embodiments, the processor102includes cache memory104. Depending on the architecture, the processor102can have a single internal cache or multiple levels of internal cache. In some embodiments, the cache memory is shared among various components of the processor102. In some embodiments, the processor102also uses an external cache (e.g., a Level-3 (L3) cache or Last Level Cache (LLC)) (not shown), which may be shared among processor cores107using known cache coherency techniques. A register file106is additionally included in processor102which may include different types of registers for storing different types of data (e.g., integer registers, floating-point registers, status registers, and an instruction pointer register). Some registers may be general-purpose registers, while other registers may be specific to the design of the processor102.

In some embodiments, one or more processor(s)102are coupled with one or more interface bus(es)110to transmit communication signals such as address, data, or control signals between processor102and other components in the system100. The interface bus110, in one embodiment, can be a processor bus, such as a version of the Direct Media Interface (DMI) bus. However, processor busses are not limited to the DMI bus, and may include one or more Peripheral Component Interconnect buses (e.g., PCI, PCI Express), memory busses, or other types of interface busses. In one embodiment the processor(s)102include an integrated memory controller116and a platform controller hub130. The memory controller116facilitates communication between a memory device and other components of the system100, while the platform controller hub (PCH)130provides connections to I/O devices via a local I/O bus.

The memory device120can be a dynamic random-access memory (DRAM) device, a static random-access memory (SRAM) device, flash memory device, phase-change memory device, or some other memory device having suitable performance to serve as process memory. In one embodiment the memory device120can operate as system memory for the system100, to store data122and instructions121for use when the one or more processors102executes an application or process. Memory controller116also couples with an optional external graphics processor112, which may communicate with the one or more graphics processors108in processors102to perform graphics and media operations. In some embodiments a display device111can connect to the processor(s)102. The display device111can be one or more of an internal display device, as in a mobile electronic device or a laptop device or an external display device attached via a display interface (e.g., DisplayPort, etc.). In one embodiment the display device111can be a head mounted display (HMD) such as a stereoscopic display device for use in virtual reality (VR) applications or augmented reality (AR) applications.

In some embodiments the platform controller hub130enables peripherals to connect to memory device120and processor102via a high-speed I/O bus. The I/O peripherals include, but are not limited to, an audio controller146, a network controller134, a firmware interface128, a wireless transceiver126, touch sensors125, a data storage device124(e.g., hard disk drive, flash memory, etc.). The data storage device124can connect via a storage interface (e.g., SATA) or via a peripheral bus, such as a Peripheral Component Interconnect bus (e.g., PCI, PCI Express). The touch sensors125can include touch screen sensors, pressure sensors, or fingerprint sensors. The wireless transceiver126can be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver such as a 3G, 4G, or Long-Term Evolution (LTE) transceiver. The firmware interface128enables communication with system firmware, and can be, for example, a unified extensible firmware interface (UEFI). The network controller134can enable a network connection to a wired network. In some embodiments, a high-performance network controller (not shown) couples with the interface bus110. The audio controller146, in one embodiment, is a multi-channel high definition audio controller. In one embodiment the system100includes an optional legacy I/O controller140for coupling legacy (e.g., Personal System 2 (PS/2)) devices to the system. The platform controller hub130can also connect to one or more Universal Serial Bus (USB) controllers142connect input devices, such as keyboard and mouse143combinations, a camera144, or other USB input devices.

It will be appreciated that the system100shown is exemplary and not limiting, as other types of data processing systems that are differently configured may also be used. For example, an instance of the memory controller116and platform controller hub130may be integrated into a discreet external graphics processor, such as the external graphics processor112. In one embodiment the platform controller hub130and/or memory controller160may be external to the one or more processor(s)102. For example, the system100can include an external memory controller116and platform controller hub130, which may be configured as a memory controller hub and peripheral controller hub within a system chipset that is in communication with the processor(s)102.

FIG. 2is a block diagram of an embodiment of a processor200having one or more processor cores202A-202N, an integrated memory controller214, and an integrated graphics processor208. Those elements ofFIG. 2having the same reference numbers (or names) as the elements of any other figure herein can operate or function in any manner similar to that described elsewhere herein but are not limited to such. Processor200can include additional cores up to and including additional core202N represented by the dashed lined boxes. Each of processor cores202A-202N includes one or more internal cache units204A-204N. In some embodiments each processor core also has access to one or more shared cached units206.

The internal cache units204A-204N and shared cache units206represent a cache memory hierarchy within the processor200. The cache memory hierarchy may include at least one level of instruction and data cache within each processor core and one or more levels of shared mid-level cache, such as a Level 2 (L2), Level 3 (L3), Level 4 (L4), or other levels of cache, where the highest level of cache before external memory is classified as the LLC. In some embodiments, cache coherency logic maintains coherency between the various cache units206and204A-204N.

In some embodiments, processor200may also include a set of one or more bus controller units216and a system agent core210. The one or more bus controller units216manage a set of peripheral buses, such as one or more PCI or PCI express busses. System agent core210provides management functionality for the various processor components. In some embodiments, system agent core210includes one or more integrated memory controllers214to manage access to various external memory devices (not shown).

In some embodiments, one or more of the processor cores202A-202N include support for simultaneous multi-threading. In such embodiment, the system agent core210includes components for coordinating and operating cores202A-202N during multi-threaded processing. System agent core210may additionally include a power control unit (PCU), which includes logic and components to regulate the power state of processor cores202A-202N and graphics processor208.

In some embodiments, processor200additionally includes graphics processor208to execute graphics processing operations. In some embodiments, the graphics processor208couples with the set of shared cache units206, and the system agent core210, including the one or more integrated memory controllers214. In some embodiments, the system agent core210also includes a display controller211to drive graphics processor output to one or more coupled displays. In some embodiments, display controller211may also be a separate module coupled with the graphics processor via at least one interconnect or may be integrated within the graphics processor208.

In some embodiments, a ring-based interconnect unit212is used to couple the internal components of the processor200. However, an alternative interconnect unit may be used, such as a point-to-point interconnect, a switched interconnect, or other techniques, including techniques well known in the art. In some embodiments, graphics processor208couples with the ring interconnect212via an I/O link213.

The exemplary I/O link213represents at least one of multiple varieties of I/O interconnects, including an on package I/O interconnect which facilitates communication between various processor components and a high-performance embedded memory module218, such as an eDRAM module. In some embodiments, each of the processor cores202A-202N and graphics processor208use embedded memory modules218as a shared Last Level Cache.

In some embodiments, processor cores202A-202N are homogenous cores executing the same instruction set architecture. In another embodiment, processor cores202A-202N are heterogeneous in terms of instruction set architecture (ISA), where one or more of processor cores202A-202N execute a first instruction set, while at least one of the other cores executes a subset of the first instruction set or a different instruction set. In one embodiment processor cores202A-202N are heterogeneous in terms of microarchitecture, where one or more cores having a relatively higher power consumption couple with one or more power cores having a lower power consumption. Additionally, processor200can be implemented on one or more chips or as an SoC integrated circuit having the illustrated components, in addition to other components.

FIG. 3is a block diagram of a graphics processor300, which may be a discrete graphics processing unit, or may be a graphics processor integrated with a plurality of processing cores. In some embodiments, the graphics processor communicates via a memory mapped I/O interface to registers on the graphics processor and with commands placed into the processor memory. In some embodiments, graphics processor300includes a memory interface314to access memory. Memory interface314can be an interface to local memory, one or more internal caches, one or more shared external caches, and/or to system memory.

In some embodiments, graphics processor300also includes a display controller302to drive display output data to a display device320. Display controller302includes hardware for one or more overlay planes for the display and composition of multiple layers of video or user interface elements. The display device320can be an internal or external display device. In one embodiment the display device320is a head mounted display device, such as a virtual reality (VR) display device or an augmented reality (AR) display device. In some embodiments, graphics processor300includes a video codec engine306to encode, decode, or transcode media to, from, or between one or more media encoding formats, including, but not limited to Moving Picture Experts Group (MPEG) formats such as MPEG-2, Advanced Video Coding (AVC) formats such as H.264/MPEG-4 AVC, as well as the Society of Motion Picture & Television Engineers (SMPTE) 421M/VC-1, and Joint Photographic Experts Group (JPEG) formats such as JPEG, and Motion JPEG (MJPEG) formats.

In some embodiments, graphics processor300includes a block image transfer (BLIT) engine304to perform two-dimensional (2D) rasterizer operations including, for example, bit-boundary block transfers. However, in one embodiment, 2D graphics operations are performed using one or more components of graphics processing engine (GPE)310. In some embodiments, GPE310is a compute engine for performing graphics operations, including three-dimensional (3D) graphics operations and media operations.

In some embodiments, GPE310includes a 3D pipeline312for performing 3D operations, such as rendering three-dimensional images and scenes using processing functions that act upon 3D primitive shapes (e.g., rectangle, triangle, etc.). The 3D pipeline312includes programmable and fixed function elements that perform various tasks within the element and/or spawn execution threads to a 3D/Media sub-system315. While 3D pipeline312can be used to perform media operations, an embodiment of GPE310also includes a media pipeline316that is specifically used to perform media operations, such as video post-processing and image enhancement.

In some embodiments, media pipeline316includes fixed function or programmable logic units to perform one or more specialized media operations, such as video decode acceleration, video de-interlacing, and video encode acceleration in place of, or on behalf of video codec engine306. In some embodiments, media pipeline316additionally includes a thread spawning unit to spawn threads for execution on 3D/Media sub-system315. The spawned threads perform computations for the media operations on one or more graphics execution units included in 3D/Media sub-system315.

In some embodiments, 3D/Media subsystem315includes logic for executing threads spawned by 3D pipeline312and media pipeline316. In one embodiment, the pipelines send thread execution requests to 3D/Media subsystem315, which includes thread dispatch logic for arbitrating and dispatching the various requests to available thread execution resources. The execution resources include an array of graphics execution units to process the 3D and media threads. In some embodiments, 3D/Media subsystem315includes one or more internal caches for thread instructions and data. In some embodiments, the subsystem also includes shared memory, including registers and addressable memory, to share data between threads and to store output data.

Graphics Processing Engine

FIG. 4is a block diagram of a graphics processing engine410of a graphics processor in accordance with some embodiments. In one embodiment, the graphics processing engine (GPE)410is a version of the GPE310shown inFIG. 3. Elements ofFIG. 4having the same reference numbers (or names) as the elements of any other figure herein can operate or function in any manner similar to that described elsewhere herein, but are not limited to such. For example, the 3D pipeline312and media pipeline316ofFIG. 3are illustrated. The media pipeline316is optional in some embodiments of the GPE410and may not be explicitly included within the GPE410. For example, and in at least one embodiment, a separate media and/or image processor is coupled to the GPE410.

In some embodiments, GPE410couples with or includes a command streamer403, which provides a command stream to the 3D pipeline312and/or media pipelines316. In some embodiments, command streamer403is coupled with memory, which can be system memory, or one or more of internal cache memory and shared cache memory. In some embodiments, command streamer403receives commands from the memory and sends the commands to 3D pipeline312and/or media pipeline316. The commands are directives fetched from a ring buffer, which stores commands for the 3D pipeline312and media pipeline316. In one embodiment, the ring buffer can additionally include batch command buffers storing batches of multiple commands. The commands for the 3D pipeline312can also include references to data stored in memory, such as but not limited to vertex and geometry data for the 3D pipeline312and/or image data and memory objects for the media pipeline316. The 3D pipeline312and media pipeline316process the commands and data by performing operations via logic within the respective pipelines or by dispatching one or more execution threads to a graphics core array414. In one embodiment the graphics core array414include one or more blocks of graphics cores (e.g., graphics core(s)415A, graphics core(s)415B), each block including one or more graphics cores. Each graphics core includes a set of graphics execution resources that includes general purpose and graphics specific execution logic to perform graphics and compute operations, as well as fixed function texture processing and/or machine learning and artificial intelligence acceleration logic.

In various embodiments the 3D pipeline312includes fixed function and programmable logic to process one or more shader programs, such as vertex shaders, geometry shaders, pixel shaders, fragment shaders, compute shaders, or other shader programs, by processing the instructions and dispatching execution threads to the graphics core array414. The graphics core array414provides a unified block of execution resources for use in processing these shader programs. Multi-purpose execution logic (e.g., execution units) within the graphics core(s)415A-414B of the graphic core array414includes support for various 3D API shader languages and can execute multiple simultaneous execution threads associated with multiple shaders.

In some embodiments the graphics core array414also includes execution logic to perform media functions, such as video and/or image processing. In one embodiment, the execution units additionally include general-purpose logic that is programmable to perform parallel general purpose computational operations, in addition to graphics processing operations. The general-purpose logic can perform processing operations in parallel or in conjunction with general purpose logic within the processor core(s)107ofFIG. 1or core202A-202N as inFIG. 2.

Output data generated by threads executing on the graphics core array414can output data to memory in a unified return buffer (URB)418. The URB418can store data for multiple threads. In some embodiments the URB418may be used to send data between different threads executing on the graphics core array414. In some embodiments the URB418may additionally be used for synchronization between threads on the graphics core array and fixed function logic within the shared function logic420.

In some embodiments, graphics core array414is scalable, such that the array includes a variable number of graphics cores, each having a variable number of execution units based on the target power and performance level of GPE410. In one embodiment the execution resources are dynamically scalable, such that execution resources may be enabled or disabled as needed.

The graphics core array414couples with shared function logic420that includes multiple resources that are shared between the graphics cores in the graphics core array. The shared functions within the shared function logic420are hardware logic units that provide specialized supplemental functionality to the graphics core array414. In various embodiments, shared function logic420includes but is not limited to sampler421, math422, and inter-thread communication (ITC)423logic. Additionally, some embodiments implement one or more cache(s)425within the shared function logic420.

A shared function is implemented where the demand for a given specialized function is insufficient for inclusion within the graphics core array414. Instead a single instantiation of that specialized function is implemented as a stand-alone entity in the shared function logic420and shared among the execution resources within the graphics core array414. The precise set of functions that are shared between the graphics core array414and included within the graphics core array414varies across embodiments. In some embodiments, specific shared functions within the shared function logic420that are used extensively by the graphics core array414may be included within shared function logic416within the graphics core array414. In various embodiments, the shared function logic416within the graphics core array414can include some or all logic within the shared function logic420. In one embodiment, all logic elements within the shared function logic420may be duplicated within the shared function logic416of the graphics core array414. In one embodiment the shared function logic420is excluded in favor of the shared function logic416within the graphics core array414.

FIG. 5is a block diagram of hardware logic of a graphics processor core500, according to some embodiments described herein. Elements ofFIG. 5having the same reference numbers (or names) as the elements of any other figure herein can operate or function in any manner similar to that described elsewhere herein, but are not limited to such. The illustrated graphics processor core500, in some embodiments, is included within the graphics core array414ofFIG. 4. The graphics processor core500, sometimes referred to as a core slice, can be one or multiple graphics cores within a modular graphics processor. The graphics processor core500is exemplary of one graphics core slice, and a graphics processor as described herein may include multiple graphics core slices based on target power and performance envelopes. Each graphics core500can include a fixed function block530coupled with multiple sub-cores501A-501F, also referred to as sub-slices, that include modular blocks of general purpose and fixed function logic.

In some embodiments the fixed function block530includes a geometry/fixed function pipeline536that can be shared by all sub-cores in the graphics processor500, for example, in lower performance and/or lower power graphics processor implementations. In various embodiments, the geometry/fixed function pipeline536includes a 3D fixed function pipeline (e.g., 3D pipeline312as inFIG. 3andFIG. 4) a video front-end unit, a thread spawner and thread dispatcher, and a unified return buffer manager, which manages unified return buffers, such as the unified return buffer418ofFIG. 4.

In one embodiment the fixed function block530also includes a graphics SoC interface537, a graphics microcontroller538, and a media pipeline539. The graphics SoC interface537provides an interface between the graphics core500and other processor cores within a system on a chip integrated circuit. The graphics microcontroller538is a programmable sub-processor that is configurable to manage various functions of the graphics processor500, including thread dispatch, scheduling, and pre-emption. The media pipeline539(e.g., media pipeline316ofFIG. 3andFIG. 4) includes logic to facilitate the decoding, encoding, pre-processing, and/or post-processing of multimedia data, including image and video data. The media pipeline539implement media operations via requests to compute or sampling logic within the sub-cores501-501F.

In one embodiment the SoC interface537enables the graphics core500to communicate with general purpose application processor cores (e.g., CPUs) and/or other components within an SoC, including memory hierarchy elements such as a shared last level cache memory, the system RAM, and/or embedded on-chip or on-package DRAM. The SoC interface537can also enable communication with fixed function devices within the SoC, such as camera imaging pipelines, and enables the use of and/or implements global memory atomics that may be shared between the graphics core500and CPUs within the SoC. The SoC interface537can also implement power management controls for the graphics core500and enable an interface between a clock domain of the graphic core500and other clock domains within the SoC. In one embodiment the SoC interface537enables receipt of command buffers from a command streamer and global thread dispatcher that are configured to provide commands and instructions to each of one or more graphics cores within a graphics processor. The commands and instructions can be dispatched to the media pipeline539, when media operations are to be performed, or a geometry and fixed function pipeline (e.g., geometry and fixed function pipeline536, geometry and fixed function pipeline514) when graphics processing operations are to be performed.

The graphics microcontroller538can be configured to perform various scheduling and management tasks for the graphics core500. In one embodiment the graphics microcontroller538can perform graphics and/or compute workload scheduling on the various graphics parallel engines within execution unit (EU) arrays502A-502F,504A-504F within the sub-cores501A-501F. In this scheduling model, host software executing on a CPU core of an SoC including the graphics core500can submit workloads one of multiple graphic processor doorbells, which invokes a scheduling operation on the appropriate graphics engine. Scheduling operations include determining which workload to run next, submitting a workload to a command streamer, pre-empting existing workloads running on an engine, monitoring progress of a workload, and notifying host software when a workload is complete. In one embodiment the graphics microcontroller538can also facilitate low-power or idle states for the graphics core500, providing the graphics core500with the ability to save and restore registers within the graphics core500across low-power state transitions independently from the operating system and/or graphics driver software on the system.

The graphics core500may have greater than or fewer than the illustrated sub-cores501A-501F, up to N modular sub-cores. For each set of N sub-cores, the graphics core500can also include shared function logic510, shared and/or cache memory512, a geometry/fixed function pipeline514, as well as additional fixed function logic516to accelerate various graphics and compute processing operations. The shared function logic510can include logic units associated with the shared function logic420ofFIG. 4(e.g., sampler, math, and/or inter-thread communication logic) that can be shared by each N sub-cores within the graphics core500. The shared and/or cache memory512can be a last-level cache for the set of N sub-cores501A-501F within the graphics core500, and can also serve as shared memory that is accessible by multiple sub-cores. The geometry/fixed function pipeline514can be included instead of the geometry/fixed function pipeline536within the fixed function block530and can include the same or similar logic units.

In one embodiment the graphics core500includes additional fixed function logic516that can include various fixed function acceleration logic for use by the graphics core500. In one embodiment the additional fixed function logic516includes an additional geometry pipeline for use in position only shading. In position-only shading, two geometry pipelines exist, the full geometry pipeline within the geometry/fixed function pipeline516,536, and a cull pipeline, which is an additional geometry pipeline which may be included within the additional fixed function logic516. In one embodiment the cull pipeline is a trimmed down version of the full geometry pipeline. The full pipeline and the cull pipeline can execute different instances of the same application, each instance having a separate context. Position only shading can hide long cull runs of discarded triangles, enabling shading to be completed earlier in some instances. For example, and in one embodiment the cull pipeline logic within the additional fixed function logic516can execute position shaders in parallel with the main application and generally generates critical results faster than the full pipeline, as the cull pipeline fetches and shades only the position attribute of the vertices, without performing rasterization and rendering of the pixels to the frame buffer. The cull pipeline can use the generated critical results to compute visibility information for all the triangles without regard to whether those triangles are culled. The full pipeline (which in this instance may be referred to as a replay pipeline) can consume the visibility information to skip the culled triangles to shade only the visible triangles that are finally passed to the rasterization phase.

In one embodiment the additional fixed function logic516can also include machine-learning acceleration logic, such as fixed function matrix multiplication logic, for implementations including optimizations for machine learning training or inferencing.

Within each graphics sub-core501A-501F includes a set of execution resources that may be used to perform graphics, media, and compute operations in response to requests by graphics pipeline, media pipeline, or shader programs. The graphics sub-cores501A-501F include multiple EU arrays502A-502F,504A-504F, thread dispatch and inter-thread communication (TD/IC) logic503A-503F, a 3D (e.g., texture) sampler505A-505F, a media sampler506A-506F, a shader processor507A-507F, and shared local memory (SLM)508A-508F. The EU arrays502A-502F,504A-504F each include multiple execution units, which are general-purpose graphics processing units capable of performing floating-point and integer/fixed-point logic operations in service of a graphics, media, or compute operation, including graphics, media, or compute shader programs. The TD/IC logic503A-503F performs local thread dispatch and thread control operations for the execution units within a sub-core and facilitate communication between threads executing on the execution units of the sub-core. The 3D sampler505A-505F can read texture or other 3D graphics related data into memory. The 3D sampler can read texture data differently based on a configured sample state and the texture format associated with a given texture. The media sampler506A-506F can perform similar read operations based on the type and format associated with media data. In one embodiment, each graphics sub-core501A-501F can alternately include a unified 3D and media sampler. Threads executing on the execution units within each of the sub-cores501A-501F can make use of shared local memory508A-508F within each sub-core, to enable threads executing within a thread group to execute using a common pool of on-chip memory.

Execution Units

FIGS. 6A-6Billustrate thread execution logic600including an array of processing elements employed in a graphics processor core according to embodiments described herein. Elements ofFIGS. 6A-6Bhaving the same reference numbers (or names) as the elements of any other figure herein can operate or function in any manner similar to that described elsewhere herein, but are not limited to such.FIG. 6Aillustrates an overview of thread execution logic600, which can include a variant of the hardware logic illustrated with each sub-core501A-501F ofFIG. 5.FIG. 6Billustrates exemplary internal details of an execution unit.

As illustrated inFIG. 6A, in some embodiments thread execution logic600includes a shader processor602, a thread dispatcher604, instruction cache606, a scalable execution unit array including a plurality of execution units608A-608N, a sampler610, a data cache612, and a data port614. In one embodiment the scalable execution unit array can dynamically scale by enabling or disabling one or more execution units (e.g., any of execution unit608A,608B,608C,608D, through608N-1and608N) based on the computational requirements of a workload. In one embodiment the included components are interconnected via an interconnect fabric that links to each of the components. In some embodiments, thread execution logic600includes one or more connections to memory, such as system memory or cache memory, through one or more of instruction cache606, data port614, sampler610, and execution units608A-608N. In some embodiments, each execution unit (e.g.608A) is a stand-alone programmable general purpose computational unit that is capable of executing multiple simultaneous hardware threads while processing multiple data elements in parallel for each thread. In various embodiments, the array of execution units608A-608N is scalable to include any number individual execution units.

In some embodiments, the execution units608A-608N are primarily used to execute shader programs. A shader processor602can process the various shader programs and dispatch execution threads associated with the shader programs via a thread dispatcher604. In one embodiment the thread dispatcher includes logic to arbitrate thread initiation requests from the graphics and media pipelines and instantiate the requested threads on one or more execution unit in the execution units608A-608N. For example, a geometry pipeline can dispatch vertex, tessellation, or geometry shaders to the thread execution logic for processing. In some embodiments, thread dispatcher604can also process runtime thread spawning requests from the executing shader programs.

In some embodiments, the execution units608A-608N support an instruction set that includes native support for many standard 3D graphics shader instructions, such that shader programs from graphics libraries (e.g., Direct 3D and OpenGL) are executed with a minimal translation. The execution units support vertex and geometry processing (e.g., vertex programs, geometry programs, vertex shaders), pixel processing (e.g., pixel shaders, fragment shaders) and general-purpose processing (e.g., compute and media shaders). Each of the execution units608A-608N is capable of multi-issue single instruction multiple data (SIMD) execution and multi-threaded operation enables an efficient execution environment in the face of higher latency memory accesses. Each hardware thread within each execution unit has a dedicated high-bandwidth register file and associated independent thread-state. Execution is multi-issue per clock to pipelines capable of integer, single and double precision floating-point operations, SIMD branch capability, logical operations, transcendental operations, and other miscellaneous operations. While waiting for data from memory or one of the shared functions, dependency logic within the execution units608A-608N causes a waiting thread to sleep until the requested data has been returned. While the waiting thread is sleeping, hardware resources may be devoted to processing other threads. For example, during a delay associated with a vertex shader operation, an execution unit can perform operations for a pixel shader, fragment shader, or another type of shader program, including a different vertex shader.

Each execution unit in execution units608A-608N operates on arrays of data elements. The number of data elements is the “execution size,” or the number of channels for the instruction. An execution channel is a logical unit of execution for data element access, masking, and flow control within instructions. The number of channels may be independent of the number of physical Arithmetic Logic Units (ALUs) or Floating-point Units (FPUs) for a particular graphics processor. In some embodiments, execution units608A-608N support integer and floating-point data types.

The execution unit instruction set includes SIMD instructions. The various data elements can be stored as a packed data type in a register and the execution unit will process the various elements based on the data size of the elements. For example, when operating on a 256-bit wide vector, the 256 bits of the vector are stored in a register and the execution unit operates on the vector as four separate 64-bit packed data elements (Quad-Word (QW) size data elements), eight separate 32-bit packed data elements (Double Word (DW) size data elements), sixteen separate 16-bit packed data elements (Word (W) size data elements), or thirty-two separate 8-bit data elements (byte (B) size data elements). However, different vector widths and register sizes are possible.

In one embodiment one or more execution units can be combined into a fused execution unit609A-609N having thread control logic (607A-607N) that is common to the fused EUs. Multiple EUs can be fused into an EU group. Each EU in the fused EU group can be configured to execute a separate SIMD hardware thread. The number of EUs in a fused EU group can vary according to embodiments. Additionally, various SIMD widths can be performed per-EU, including but not limited to SIMD8, SIMD16, and SIMD32. Each fused graphics execution unit609A-609N includes at least two execution units. For example, fused execution unit609A includes a first EU608A, second EU608B, and thread control logic607A that is common to the first EU608A and the second EU608B. The thread control logic607A controls threads executed on the fused graphics execution unit609A, allowing each EU within the fused execution units609A-609N to execute using a common instruction pointer register.

One or more internal instruction caches (e.g.,606) are included in the thread execution logic600to cache thread instructions for the execution units. In some embodiments, one or more data caches (e.g.,612) are included to cache thread data during thread execution. In some embodiments, a sampler610is included to provide texture sampling for 3D operations and media sampling for media operations. In some embodiments, sampler610includes specialized texture or media sampling functionality to process texture or media data during the sampling process before providing the sampled data to an execution unit.

During execution, the graphics and media pipelines send thread initiation requests to thread execution logic600via thread spawning and dispatch logic. Once a group of geometric objects has been processed and rasterized into pixel data, pixel processor logic (e.g., pixel shader logic, fragment shader logic, etc.) within the shader processor602is invoked to further compute output information and cause results to be written to output surfaces (e.g., color buffers, depth buffers, stencil buffers, etc.). In some embodiments, a pixel shader or fragment shader calculates the values of the various vertex attributes that are to be interpolated across the rasterized object. In some embodiments, pixel processor logic within the shader processor602then executes an application programming interface (API)-supplied pixel or fragment shader program. To execute the shader program, the shader processor602dispatches threads to an execution unit (e.g.,608A) via thread dispatcher604. In some embodiments, shader processor602uses texture sampling logic in the sampler610to access texture data in texture maps stored in memory. Arithmetic operations on the texture data and the input geometry data compute pixel color data for each geometric fragment, or discards one or more pixels from further processing.

In some embodiments, the data port614provides a memory access mechanism for the thread execution logic600to output processed data to memory for further processing on a graphics processor output pipeline. In some embodiments, the data port614includes or couples to one or more cache memories (e.g., data cache612) to cache data for memory access via the data port.

As illustrated inFIG. 6B, a graphics execution unit608can include an instruction fetch unit637, a general register file array (GRF)624, an architectural register file array (ARF)626, a thread arbiter622, a send unit630, a branch unit632, a set of SIMD floating-point units (FPUs)634, and in one embodiment a set of dedicated integer SIMD ALUs635. The GRF624and ARF626includes the set of general register files and architecture register files associated with each simultaneous hardware thread that may be active in the graphics execution unit608. In one embodiment, per thread architectural state is maintained in the ARF626, while data used during thread execution is stored in the GRF624. The execution state of each thread, including the instruction pointers for each thread, can be held in thread-specific registers in the ARF626.

In one embodiment the graphics execution unit608has an architecture that is a combination of Simultaneous Multi-Threading (SMT) and fine-grained Interleaved Multi-Threading (IMT). The architecture has a modular configuration that can be fine-tuned at design time based on a target number of simultaneous threads and number of registers per execution unit, where execution unit resources are divided across logic used to execute multiple simultaneous threads.

In one embodiment, the graphics execution unit608can co-issue multiple instructions, which may each be different instructions. The thread arbiter622of the graphics execution unit thread608can dispatch the instructions to one of the send unit630, branch unit642, or SIMD FPU(s)634for execution. Each execution thread can access 128 general-purpose registers within the GRF624, where each register can store 32 bytes, accessible as a SIMD 8-element vector of 32-bit data elements. In one embodiment, each execution unit thread has access to 4 Kbytes within the GRF624, although embodiments are not so limited, and greater or fewer register resources may be provided in other embodiments. In one embodiment up to seven threads can execute simultaneously, although the number of threads per execution unit can also vary according to embodiments. In an embodiment in which seven threads may access 4 Kbytes, the GRF624can store a total of 28 Kbytes. Flexible addressing modes can permit registers to be addressed together to build effectively wider registers or to represent strided rectangular block data structures.

In one embodiment, memory operations, sampler operations, and other longer-latency system communications are dispatched via “send” instructions that are executed by the message passing send unit630. In one embodiment, branch instructions are dispatched to a dedicated branch unit632to facilitate SIMD divergence and eventual convergence.

In one embodiment the graphics execution unit608includes one or more SIMD floating-point units (FPU(s))634to perform floating-point operations. In one embodiment, the FPU(s)634also support integer computation. In one embodiment the FPU(s)634can SIMD execute up to M number of 32-bit floating-point (or integer) operations, or SIMD execute up to 2M 16-bit integer or 16-bit floating-point operations. In one embodiment, at least one of the FPU(s) provides extended math capability to support high-throughput transcendental math functions and double precision 64-bit floating-point. In some embodiments, a set of 8-bit integer SIMD ALUs635are also present, and may be specifically optimized to perform operations associated with machine learning computations.

In one embodiment, arrays of multiple instances of the graphics execution unit608can be instantiated in a graphics sub-core grouping (e.g., a sub-slice). For scalability, product architects can choose the exact number of execution units per sub-core grouping. In one embodiment the execution unit608can execute instructions across a plurality of execution channels. In a further embodiment, each thread executed on the graphics execution unit608is executed on a different channel.

FIG. 7is a block diagram illustrating a graphics processor instruction formats700according to some embodiments. In one or more embodiment, the graphics processor execution units support an instruction set having instructions in multiple formats. The solid lined boxes illustrate the components that are generally included in an execution unit instruction, while the dashed lines include components that are optional or that are only included in a sub-set of the instructions. In some embodiments, instruction format700described and illustrated are macro-instructions, in that they are instructions supplied to the execution unit, as opposed to micro-operations resulting from instruction decode once the instruction is processed.

In some embodiments, the graphics processor execution units natively support instructions in a 128-bit instruction format710. A 64-bit compacted instruction format730is available for some instructions based on the selected instruction, instruction options, and number of operands. The native 128-bit instruction format710provides access to all instruction options, while some options and operations are restricted in the 64-bit format730. The native instructions available in the 64-bit format730vary by embodiment. In some embodiments, the instruction is compacted in part using a set of index values in an index field713. The execution unit hardware references a set of compaction tables based on the index values and uses the compaction table outputs to reconstruct a native instruction in the 128-bit instruction format710.

For each format, instruction opcode712defines the operation that the execution unit is to perform. The execution units execute each instruction in parallel across the multiple data elements of each operand. For example, in response to an add instruction the execution unit performs a simultaneous add operation across each color channel representing a texture element or picture element. By default, the execution unit performs each instruction across all data channels of the operands. In some embodiments, instruction control field714enables control over certain execution options, such as channels selection (e.g., predication) and data channel order (e.g., swizzle). For instructions in the 128-bit instruction format710an exec-size field716limits the number of data channels that will be executed in parallel. In some embodiments, exec-size field716is not available for use in the 64-bit compact instruction format730.

Some execution unit instructions have up to three operands including two source operands, src0720, src1722, and one destination718. In some embodiments, the execution units support dual destination instructions, where one of the destinations is implied. Data manipulation instructions can have a third source operand (e.g., SRC2724), where the instruction opcode712determines the number of source operands. An instruction's last source operand can be an immediate (e.g., hard-coded) value passed with the instruction.

In some embodiments, the 128-bit instruction format710includes an access/address mode field726specifying, for example, whether direct register addressing mode or indirect register addressing mode is used. When direct register addressing mode is used, the register address of one or more operands is directly provided by bits in the instruction.

In some embodiments, the 128-bit instruction format710includes an access/address mode field726, which specifies an address mode and/or an access mode for the instruction. In one embodiment the access mode is used to define a data access alignment for the instruction. Some embodiments support access modes including a 16-byte aligned access mode and a 1-byte aligned access mode, where the byte alignment of the access mode determines the access alignment of the instruction operands. For example, when in a first mode, the instruction may use byte-aligned addressing for source and destination operands and when in a second mode, the instruction may use 16-byte-aligned addressing for all source and destination operands.

In one embodiment, the address mode portion of the access/address mode field726determines whether the instruction is to use direct or indirect addressing. When direct register addressing mode is used bits in the instruction directly provide the register address of one or more operands. When indirect register addressing mode is used, the register address of one or more operands may be computed based on an address register value and an address immediate field in the instruction.

In some embodiments instructions are grouped based on opcode712bit-fields to simplify Opcode decode740. For an 8-bit opcode, bits4,5, and6allow the execution unit to determine the type of opcode. The precise opcode grouping shown is merely an example. In some embodiments, a move and logic opcode group742includes data movement and logic instructions (e.g., move (mov), compare (cmp)). In some embodiments, move and logic group742shares the five most significant bits (MSB), where move (mov) instructions are in the form of 0000xxxxb and logic instructions are in the form of 0001xxxxb. A flow control instruction group744(e.g., call, jump (jmp)) includes instructions in the form of 0010xxxxb (e.g., 0x20). A miscellaneous instruction group746includes a mix of instructions, including synchronization instructions (e.g., wait, send) in the form of 0011xxxxb (e.g., 0x30). A parallel math instruction group748includes component-wise arithmetic instructions (e.g., add, multiply (mul)) in the form of 0100xxxxb (e.g., 0x40). The parallel math group748performs the arithmetic operations in parallel across data channels. The vector math group750includes arithmetic instructions (e.g., dp4) in the form of 0101xxxxb (e.g., 0x50). The vector math group performs arithmetic such as dot product calculations on vector operands.

Graphics Pipeline

FIG. 8is a block diagram of another embodiment of a graphics processor800. Elements ofFIG. 8having the same reference numbers (or names) as the elements of any other figure herein can operate or function in any manner similar to that described elsewhere herein, but are not limited to such.

In some embodiments, graphics processor800includes a geometry pipeline820, a media pipeline830, a display engine840, thread execution logic850, and a render output pipeline870. In some embodiments, graphics processor800is a graphics processor within a multi-core processing system that includes one or more general purpose processing cores. The graphics processor is controlled by register writes to one or more control registers (not shown) or via commands issued to graphics processor800via a ring interconnect802. In some embodiments, ring interconnect802couples graphics processor800to other processing components, such as other graphics processors or general-purpose processors. Commands from ring interconnect802are interpreted by a command streamer803, which supplies instructions to individual components of the geometry pipeline820or the media pipeline830.

In some embodiments, command streamer803directs the operation of a vertex fetcher805that reads vertex data from memory and executes vertex-processing commands provided by command streamer803. In some embodiments, vertex fetcher805provides vertex data to a vertex shader807, which performs coordinate space transformation and lighting operations to each vertex. In some embodiments, vertex fetcher805and vertex shader807execute vertex-processing instructions by dispatching execution threads to execution units852A-852B via a thread dispatcher831.

In some embodiments, execution units852A-852B are an array of vector processors having an instruction set for performing graphics and media operations. In some embodiments, execution units852A-852B have an attached L1 cache851that is specific for each array or shared between the arrays. The cache can be configured as a data cache, an instruction cache, or a single cache that is partitioned to contain data and instructions in different partitions.

In some embodiments, geometry pipeline820includes tessellation components to perform hardware-accelerated tessellation of 3D objects. In some embodiments, a programmable hull shader811configures the tessellation operations. A programmable domain shader817provides back-end evaluation of tessellation output. A tessellator813operates at the direction of hull shader811and contains special purpose logic to generate a set of detailed geometric objects based on a coarse geometric model that is provided as input to geometry pipeline820. In some embodiments, if tessellation is not used, tessellation components (e.g., hull shader811, tessellator813, and domain shader817) can be bypassed.

In some embodiments, complete geometric objects can be processed by a geometry shader819via one or more threads dispatched to execution units852A-852B, or can proceed directly to the clipper829. In some embodiments, the geometry shader operates on entire geometric objects, rather than vertices or patches of vertices as in previous stages of the graphics pipeline. If the tessellation is disabled, the geometry shader819receives input from the vertex shader807. In some embodiments, geometry shader819is programmable by a geometry shader program to perform geometry tessellation if the tessellation units are disabled.

Before rasterization, a clipper829can process vertex data. The clipper829may be a fixed function clipper or a programmable clipper having clipping and geometry shader functions. In some embodiments, a rasterizer and depth test component873in the render output pipeline870dispatches pixel shaders to convert the geometric objects into per pixel representations. In some embodiments, pixel shader logic is included in thread execution logic850. In some embodiments, an application can bypass the rasterizer and depth test component873and access un-rasterized vertex data via a stream out unit823.

The graphics processor800has an interconnect bus, interconnect fabric, or some other interconnect mechanism that allows data and message passing amongst the major components of the processor. In some embodiments, execution units852A-852B and associated logic units (e.g., L1 cache851, sampler854, texture cache858, etc.) interconnect via a data port856to perform memory access and communicate with render output pipeline components of the processor. In some embodiments, sampler854, caches851,858and execution units852A-852B each have separate memory access paths. In one embodiment the texture cache858can also be configured as a sampler cache.

In some embodiments, render output pipeline870contains a rasterizer and depth test component873that converts vertex-based objects into an associated pixel-based representation. In some embodiments, the rasterizer logic includes a windower/masker unit to perform fixed function triangle and line rasterization. An associated render cache878and depth cache879are also available in some embodiments. A pixel operations component877performs pixel-based operations on the data, though in some instances, pixel operations associated with 2D operations (e.g. bit block image transfers with blending) are performed by the 2D engine841, or substituted at display time by the display controller843using overlay display planes. In some embodiments, a shared L3 cache875is available to all graphics components, allowing the sharing of data without the use of main system memory.

In some embodiments, graphics processor media pipeline830includes a media engine837and a video front-end834. In some embodiments, video front-end834receives pipeline commands from the command streamer803. In some embodiments, media pipeline830includes a separate command streamer. In some embodiments, video front-end834processes media commands before sending the command to the media engine837. In some embodiments, media engine837includes thread spawning functionality to spawn threads for dispatch to thread execution logic850via thread dispatcher831.

In some embodiments, graphics processor800includes a display engine840. In some embodiments, display engine840is external to processor800and couples with the graphics processor via the ring interconnect802, or some other interconnect bus or fabric. In some embodiments, display engine840includes a 2D engine841and a display controller843. In some embodiments, display engine840contains special purpose logic capable of operating independently of the 3D pipeline. In some embodiments, display controller843couples with a display device (not shown), which may be a system integrated display device, as in a laptop computer, or an external display device attached via a display device connector.

In some embodiments, the geometry pipeline820and media pipeline830are configurable to perform operations based on multiple graphics and media programming interfaces and are not specific to any one application programming interface (API). In some embodiments, driver software for the graphics processor translates API calls that are specific to a particular graphics or media library into commands that can be processed by the graphics processor. In some embodiments, support is provided for the Open Graphics Library (OpenGL), Open Computing Language (OpenCL), and/or Vulkan graphics and compute API, all from the Khronos Group. In some embodiments, support may also be provided for the Direct3D library from the Microsoft Corporation. In some embodiments, a combination of these libraries may be supported. Support may also be provided for the Open Source Computer Vision Library (OpenCV). A future API with a compatible 3D pipeline would also be supported if a mapping can be made from the pipeline of the future API to the pipeline of the graphics processor.

Graphics Pipeline Programming

FIG. 9Ais a block diagram illustrating a graphics processor command format900according to some embodiments.FIG. 9Bis a block diagram illustrating a graphics processor command sequence910according to an embodiment. The solid lined boxes inFIG. 9Aillustrate the components that are generally included in a graphics command while the dashed lines include components that are optional or that are only included in a sub-set of the graphics commands. The exemplary graphics processor command format900ofFIG. 9Aincludes data fields to identify a client902, a command operation code (opcode)904, and data906for the command. A sub-opcode905and a command size908are also included in some commands.

In some embodiments, client902specifies the client unit of the graphics device that processes the command data. In some embodiments, a graphics processor command parser examines the client field of each command to condition the further processing of the command and route the command data to the appropriate client unit. In some embodiments, the graphics processor client units include a memory interface unit, a render unit, a 2D unit, a 3D unit, and a media unit. Each client unit has a corresponding processing pipeline that processes the commands Once the command is received by the client unit, the client unit reads the opcode904and, if present, sub-opcode905to determine the operation to perform. The client unit performs the command using information in data field906. For some commands an explicit command size908is expected to specify the size of the command. In some embodiments, the command parser automatically determines the size of at least some of the commands based on the command opcode. In some embodiments commands are aligned via multiples of a double word.

The flow diagram inFIG. 9Billustrates an exemplary graphics processor command sequence910. In some embodiments, software or firmware of a data processing system that features an embodiment of a graphics processor uses a version of the command sequence shown to set up, execute, and terminate a set of graphics operations. A sample command sequence is shown and described for purposes of example only as embodiments are not limited to these specific commands or to this command sequence. Moreover, the commands may be issued as batch of commands in a command sequence, such that the graphics processor will process the sequence of commands in at least partially concurrence.

In some embodiments, the graphics processor command sequence910may begin with a pipeline flush command912to cause any active graphics pipeline to complete the currently pending commands for the pipeline. In some embodiments, the 3D pipeline922and the media pipeline924do not operate concurrently. The pipeline flush is performed to cause the active graphics pipeline to complete any pending commands In response to a pipeline flush, the command parser for the graphics processor will pause command processing until the active drawing engines complete pending operations and the relevant read caches are invalidated. Optionally, any data in the render cache that is marked ‘dirty’ can be flushed to memory. In some embodiments, pipeline flush command912can be used for pipeline synchronization or before placing the graphics processor into a low power state.

In some embodiments, a pipeline select command913is used when a command sequence requires the graphics processor to explicitly switch between pipelines. In some embodiments, a pipeline select command913is required only once within an execution context before issuing pipeline commands unless the context is to issue commands for both pipelines. In some embodiments, a pipeline flush command912is required immediately before a pipeline switch via the pipeline select command913.

In some embodiments, a pipeline control command914configures a graphics pipeline for operation and is used to program the 3D pipeline922and the media pipeline924. In some embodiments, pipeline control command914configures the pipeline state for the active pipeline. In one embodiment, the pipeline control command914is used for pipeline synchronization and to clear data from one or more cache memories within the active pipeline before processing a batch of commands.

In some embodiments, return buffer state commands916are used to configure a set of return buffers for the respective pipelines to write data. Some pipeline operations require the allocation, selection, or configuration of one or more return buffers into which the operations write intermediate data during processing. In some embodiments, the graphics processor also uses one or more return buffers to store output data and to perform cross thread communication. In some embodiments, the return buffer state916includes selecting the size and number of return buffers to use for a set of pipeline operations.

The remaining commands in the command sequence differ based on the active pipeline for operations. Based on a pipeline determination920, the command sequence is tailored to the 3D pipeline922beginning with the 3D pipeline state930or the media pipeline924beginning at the media pipeline state940.

The commands to configure the 3D pipeline state930include 3D state setting commands for vertex buffer state, vertex element state, constant color state, depth buffer state, and other state variables that are to be configured before 3D primitive commands are processed. The values of these commands are determined at least in part based on the particular 3D API in use. In some embodiments, 3D pipeline state930commands are also able to selectively disable or bypass certain pipeline elements if those elements will not be used.

In some embodiments, 3D primitive932command is used to submit 3D primitives to be processed by the 3D pipeline. Commands and associated parameters that are passed to the graphics processor via the 3D primitive932command are forwarded to the vertex fetch function in the graphics pipeline. The vertex fetch function uses the 3D primitive932command data to generate vertex data structures. The vertex data structures are stored in one or more return buffers. In some embodiments, 3D primitive932command is used to perform vertex operations on 3D primitives via vertex shaders. To process vertex shaders, 3D pipeline922dispatches shader execution threads to graphics processor execution units.

In some embodiments, 3D pipeline922is triggered via an execute934command or event. In some embodiments, a register write triggers command execution. In some embodiments execution is triggered via a ‘go’ or ‘kick’ command in the command sequence. In one embodiment, command execution is triggered using a pipeline synchronization command to flush the command sequence through the graphics pipeline. The 3D pipeline will perform geometry processing for the 3D primitives. Once operations are complete, the resulting geometric objects are rasterized and the pixel engine colors the resulting pixels. Additional commands to control pixel shading and pixel back end operations may also be included for those operations.

In some embodiments, the graphics processor command sequence910follows the media pipeline924path when performing media operations. In general, the specific use and manner of programming for the media pipeline924depends on the media or compute operations to be performed. Specific media decode operations may be offloaded to the media pipeline during media decode. In some embodiments, the media pipeline can also be bypassed, and media decode can be performed in whole or in part using resources provided by one or more general purpose processing cores. In one embodiment, the media pipeline also includes elements for general-purpose graphics processor unit (GPGPU) operations, where the graphics processor is used to perform SIMD vector operations using computational shader programs that are not explicitly related to the rendering of graphics primitives.

In some embodiments, media pipeline924is configured in a similar manner as the 3D pipeline922. A set of commands to configure the media pipeline state940are dispatched or placed into a command queue before the media object commands942. In some embodiments, commands for the media pipeline state940include data to configure the media pipeline elements that will be used to process the media objects. This includes data to configure the video decode and video encode logic within the media pipeline, such as encode or decode format. In some embodiments, commands for the media pipeline state940also support the use of one or more pointers to “indirect” state elements that contain a batch of state settings.

In some embodiments, media object commands942supply pointers to media objects for processing by the media pipeline. The media objects include memory buffers containing video data to be processed. In some embodiments, all media pipeline states must be valid before issuing a media object command942. Once the pipeline state is configured and media object commands942are queued, the media pipeline924is triggered via an execute command944or an equivalent execute event (e.g., register write). Output from media pipeline924may then be post processed by operations provided by the 3D pipeline922or the media pipeline924. In some embodiments, GPGPU operations are configured and executed in a similar manner as media operations.

Graphics Software Architecture

FIG. 10illustrates exemplary graphics software architecture for a data processing system1000according to some embodiments. In some embodiments, software architecture includes a 3D graphics application1010, an operating system1020, and at least one processor1030. In some embodiments, processor1030includes a graphics processor1032and one or more general-purpose processor core(s)1034. The graphics application1010and operating system1020each execute in the system memory1050of the data processing system.

In some embodiments, 3D graphics application1010contains one or more shader programs including shader instructions1012. The shader language instructions may be in a high-level shader language, such as the High-Level Shader Language (HLSL) or the OpenGL Shader Language (GLSL). The application also includes executable instructions1014in a machine language suitable for execution by the general-purpose processor core1034. The application also includes graphics objects1016defined by vertex data.

In some embodiments, operating system1020is a Microsoft® Windows® operating system from the Microsoft Corporation, a proprietary UNIX-like operating system, or an open source UNIX-like operating system using a variant of the Linux kernel. The operating system1020can support a graphics API1022such as the Direct3D API, the OpenGL API, or the Vulkan API. When the Direct3D API is in use, the operating system1020uses a front-end shader compiler1024to compile any shader instructions1012in HLSL into a lower-level shader language. The compilation may be a just-in-time (JIT) compilation or the application can perform shader pre-compilation. In some embodiments, high-level shaders are compiled into low-level shaders during the compilation of the 3D graphics application1010. In some embodiments, the shader instructions1012are provided in an intermediate form, such as a version of the Standard Portable Intermediate Representation (SPIR) used by the Vulkan API.

In some embodiments, user mode graphics driver1026contains a back-end shader compiler1027to convert the shader instructions1012into a hardware specific representation. When the OpenGL API is in use, shader instructions1012in the GLSL high-level language are passed to a user mode graphics driver1026for compilation. In some embodiments, user mode graphics driver1026uses operating system kernel mode functions1028to communicate with a kernel mode graphics driver1029. In some embodiments, kernel mode graphics driver1029communicates with graphics processor1032to dispatch commands and instructions.

IP Core Implementations

One or more aspects of at least one embodiment may be implemented by representative code stored on a machine-readable medium which represents and/or defines logic within an integrated circuit such as a processor. For example, the machine-readable medium may include instructions which represent various logic within the processor. When read by a machine, the instructions may cause the machine to fabricate the logic to perform the techniques described herein. Such representations, known as “IP cores,” are reusable units of logic for an integrated circuit that may be stored on a tangible, machine-readable medium as a hardware model that describes the structure of the integrated circuit. The hardware model may be supplied to various customers or manufacturing facilities, which load the hardware model on fabrication machines that manufacture the integrated circuit. The integrated circuit may be fabricated such that the circuit performs operations described in association with any of the embodiments described herein.

FIG. 11Ais a block diagram illustrating an IP core development system1100that may be used to manufacture an integrated circuit to perform operations according to an embodiment. The IP core development system1100may be used to generate modular, reusable designs that can be incorporated into a larger design or used to construct an entire integrated circuit (e.g., an SOC integrated circuit). A design facility1130can generate a software simulation1110of an IP core design in a high-level programming language (e.g., C/C++). The software simulation1110can be used to design, test, and verify the behavior of the IP core using a simulation model1112. The simulation model1112may include functional, behavioral, and/or timing simulations. A register transfer level (RTL) design1115can then be created or synthesized from the simulation model1112. The RTL design1115is an abstraction of the behavior of the integrated circuit that models the flow of digital signals between hardware registers, including the associated logic performed using the modeled digital signals. In addition to an RTL design1115, lower-level designs at the logic level or transistor level may also be created, designed, or synthesized. Thus, the particular details of the initial design and simulation may vary.

The RTL design1115or equivalent may be further synthesized by the design facility into a hardware model1120, which may be in a hardware description language (HDL), or some other representation of physical design data. The HDL may be further simulated or tested to verify the IP core design. The IP core design can be stored for delivery to a 3rdparty fabrication facility1165using non-volatile memory1140(e.g., hard disk, flash memory, or any non-volatile storage medium). Alternatively, the IP core design may be transmitted (e.g., via the Internet) over a wired connection1150or wireless connection1160. The fabrication facility1165may then fabricate an integrated circuit that is based at least in part on the IP core design. The fabricated integrated circuit can be configured to perform operations in accordance with at least one embodiment described herein.

FIG. 11Billustrates a cross-section side view of an integrated circuit package assembly1170, according to some embodiments described herein. The integrated circuit package assembly1170illustrates an implementation of one or more processor or accelerator devices as described herein. The package assembly1170includes multiple units of hardware logic1172,1174connected to a substrate1180. The logic1172,1174may be implemented at least partly in configurable logic or fixed-functionality logic hardware and can include one or more portions of any of the processor core(s), graphics processor(s), or other accelerator devices described herein. Each unit of logic1172,1174can be implemented within a semiconductor die and coupled with the substrate1180via an interconnect structure1173. The interconnect structure1173may be configured to route electrical signals between the logic1172,1174and the substrate1180, and can include interconnects such as, but not limited to bumps or pillars. In some embodiments, the interconnect structure1173may be configured to route electrical signals such as, for example, input/output (I/O) signals and/or power or ground signals associated with the operation of the logic1172,1174. In some embodiments, the substrate1180is an epoxy-based laminate substrate. The package substrate1180may include other suitable types of substrates in other embodiments. The package assembly1170can be connected to other electrical devices via a package interconnect1183. The package interconnect1183may be coupled to a surface of the substrate1180to route electrical signals to other electrical devices, such as a motherboard, other chipset, or multi-chip module.

In some embodiments, the units of logic1172,1174are electrically coupled with a bridge1182that is configured to route electrical signals between the logic1172,1174. The bridge1182may be a dense interconnect structure that provides a route for electrical signals. The bridge1182may include a bridge substrate composed of glass or a suitable semiconductor material. Electrical routing features can be formed on the bridge substrate to provide a chip-to-chip connection between the logic1172,1174.

Although two units of logic1172,1174and a bridge1182are illustrated, embodiments described herein may include more or fewer logic units on one or more dies. The one or more dies may be connected by zero or more bridges, as the bridge1182may be excluded when the logic is included on a single die. Alternatively, multiple dies or units of logic can be connected by one or more bridges. Additionally, multiple logic units, dies, and bridges can be connected together in other possible configurations, including three-dimensional configurations.

Exemplary System on a Chip Integrated Circuit

FIGS. 12-14illustrated exemplary integrated circuits and associated graphics processors that may be fabricated using one or more IP cores, according to various embodiments described herein. In addition to what is illustrated, other logic and circuits may be included, including additional graphics processors/cores, peripheral interface controllers, or general-purpose processor cores.

FIG. 12is a block diagram illustrating an exemplary system on a chip integrated circuit1200that may be fabricated using one or more IP cores, according to an embodiment. Exemplary integrated circuit1200includes one or more application processor(s)1205(e.g., CPUs), at least one graphics processor1210, and may additionally include an image processor1215and/or a video processor1220, any of which may be a modular IP core from the same or multiple different design facilities. Integrated circuit1200includes peripheral or bus logic including a USB controller1225, UART controller1230, an SPI/SDIO controller1235, and an I2S/I2C controller1240. Additionally, the integrated circuit can include a display device1245coupled to one or more of a high-definition multimedia interface (HDMI) controller1250and a mobile industry processor interface (MIPI) display interface1255. Storage may be provided by a flash memory subsystem1260including flash memory and a flash memory controller. Memory interface may be provided via a memory controller1265for access to SDRAM or SRAM memory devices. Some integrated circuits additionally include an embedded security engine1270.

FIGS. 13A-13Bare block diagrams illustrating exemplary graphics processors for use within an SoC, according to embodiments described herein.FIG. 13Aillustrates an exemplary graphics processor1310of a system on a chip integrated circuit that may be fabricated using one or more IP cores, according to an embodiment.FIG. 13Billustrates an additional exemplary graphics processor1340of a system on a chip integrated circuit that may be fabricated using one or more IP cores, according to an embodiment. Graphics processor1310ofFIG. 13Ais an example of a low power graphics processor core. Graphics processor1340ofFIG. 13Bis an example of a higher performance graphics processor core. Each of the graphics processors1310,1340can be variants of the graphics processor1210ofFIG. 12.

As shown inFIG. 13A, graphics processor1310includes a vertex processor1305and one or more fragment processor(s)1315A-1315N (e.g.,1315A,1315B,1315C,1315D, through1315N-1, and1315N). Graphics processor1310can execute different shader programs via separate logic, such that the vertex processor1305is optimized to execute operations for vertex shader programs, while the one or more fragment processor(s)1315A-1315N execute fragment (e.g., pixel) shading operations for fragment or pixel shader programs. The vertex processor1305performs the vertex processing stage of the 3D graphics pipeline and generates primitives and vertex data. The fragment processor(s)1315A-1315N use the primitive and vertex data generated by the vertex processor1305to produce a framebuffer that is displayed on a display device. In one embodiment, the fragment processor(s)1315A-1315N are optimized to execute fragment shader programs as provided for in the OpenGL API, which may be used to perform similar operations as a pixel shader program as provided for in the Direct 3D API.

Graphics processor1310additionally includes one or more memory management units (MMUs)1320A-1320B, cache(s)1325A-1325B, and circuit interconnect(s)1330A-1330B. The one or more MMU(s)1320A-1320B provide for virtual to physical address mapping for the graphics processor1310, including for the vertex processor1305and/or fragment processor(s)1315A-1315N, which may reference vertex or image/texture data stored in memory, in addition to vertex or image/texture data stored in the one or more cache(s)1325A-1325B. In one embodiment, the one or more MMU(s)1320A-1320B may be synchronized with other MMUs within the system, including one or more MMUs associated with the one or more application processor(s)1205, image processor1215, and/or video processor1220ofFIG. 12, such that each processor1205-1220can participate in a shared or unified virtual memory system. The one or more circuit interconnect(s)1330A-1330B enable graphics processor1310to interface with other IP cores within the SoC, either via an internal bus of the SoC or via a direct connection, according to embodiments.

As shownFIG. 13B, graphics processor1340includes the one or more MMU(s)1320A-1320B, caches1325A-1325B, and circuit interconnects1330A-1330B of the graphics processor1310ofFIG. 13A. Graphics processor1340includes one or more shader core(s)1355A-1355N (e.g.,1455A,1355B,1355C,1355D,1355E,1355F, through1355N-1, and1355N), which provides for a unified shader core architecture in which a single core or type or core can execute all types of programmable shader code, including shader program code to implement vertex shaders, fragment shaders, and/or compute shaders. The exact number of shader cores present can vary among embodiments and implementations. Additionally, graphics processor1340includes an inter-core task manager1345, which acts as a thread dispatcher to dispatch execution threads to one or more shader cores1355A-1355N and a tiling unit1358to accelerate tiling operations for tile-based rendering, in which rendering operations for a scene are subdivided in image space, for example to exploit local spatial coherence within a scene or to optimize use of internal caches.

FIGS. 14A-14Billustrate additional exemplary graphics processor logic according to embodiments described herein.FIG. 14Aillustrates a graphics core1400that may be included within the graphics processor1210ofFIG. 12and may be a unified shader core1355A-1355N as inFIG. 13B.FIG. 14Billustrates a highly-parallel general-purpose graphics processing unit1430suitable for deployment on a multi-chip module.

As shown inFIG. 14A, the graphics core1400includes a shared instruction cache1402, a texture unit1418, and a cache/shared memory1420that are common to the execution resources within the graphics core1400. The graphics core1400can include multiple slices1401A-1401N or partition for each core, and a graphics processor can include multiple instances of the graphics core1400. The slices1401A-1401N can include support logic including a local instruction cache1404A-1404N, a thread scheduler1406A-1406N, a thread dispatcher1408A-1408N, and a set of registers1410A. To perform logic operations, the slices1401A-1401N can include a set of additional function units (AFUs1412A-1412N), floating-point units (FPU1414A-1414N), integer arithmetic logic units (ALUs1416-1416N), address computational units (ACU1413A-1413N), double-precision floating-point units (DPFPU1415A-1415N), and matrix processing units (MPU1417A-1417N).

Some of the computational units operate at a specific precision. For example, the FPUs1414A-1414N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, while the DPFPUs1415A-1415N perform double precision (64-bit) floating-point operations. The ALUs1416A-1416N can perform variable precision integer operations at 8-bit, 16-bit, and 32-bit precision, and can be configured for mixed precision operations. The MPUs1417A-1417N can also be configured for mixed precision matrix operations, including half-precision floating-point and 8-bit integer operations. The MPUs1417-1417N can perform a variety of matrix operations to accelerate machine learning application frameworks, including enabling support for accelerated general matrix to matrix multiplication (GEMM). The AFUs1412A-1412N can perform additional logic operations not supported by the floating-point or integer units, including trigonometric operations (e.g., Sine, Cosine, etc.).

As shown inFIG. 14B, a general-purpose processing unit (GPGPU)1430can be configured to enable highly-parallel compute operations to be performed by an array of graphics processing units. Additionally, the GPGPU1430can be linked directly to other instances of the GPGPU to create a multi-GPU cluster to improve training speed for particularly deep neural networks. The GPGPU1430includes a host interface1432to enable a connection with a host processor. In one embodiment the host interface1432is a PCI Express interface. However, the host interface can also be a vendor specific communications interface or communications fabric. The GPGPU1430receives commands from the host processor and uses a global scheduler1434to distribute execution threads associated with those commands to a set of compute clusters1436A-1436H. The compute clusters1436A-1436H share a cache memory1438. The cache memory1438can serve as a higher-level cache for cache memories within the compute clusters1436A-1436H.

The GPGPU1430includes memory1434A-1434B coupled with the compute clusters1436A-1436H via a set of memory controllers1442A-1442B. In various embodiments, the memory1434A-1434B can include various types of memory devices including dynamic random-access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory.

In one embodiment, the compute clusters1436A-1436H each include a set of graphics cores, such as the graphics core1400ofFIG. 14A, which can include multiple types of integer and floating-point logic units that can perform computational operations at a range of precisions including suited for machine learning computations. For example, and in one embodiment at least a subset of the floating-point units in each of the compute clusters1436A-1436H can be configured to perform 16-bit or 32-bit floating-point operations, while a different subset of the floating-point units can be configured to perform 64-bit floating-point operations.

Multiple instances of the GPGPU1430can be configured to operate as a compute cluster. The communication mechanism used by the compute cluster for synchronization and data exchange varies across embodiments. In one embodiment, the multiple instances of the GPGPU1430communicate over the host interface1432. In one embodiment, the GPGPU1430includes an I/O hub1439that couples the GPGPU1430with a GPU link1440that enables a direct connection to other instances of the GPGPU. In one embodiment, the GPU link1440is coupled to a dedicated GPU-to-GPU bridge that enables communication and synchronization between multiple instances of the GPGPU1430. In one embodiment, the GPU link1440couples with a high-speed interconnect to transmit and receive data to other GPGPUs or parallel processors. In one embodiment the multiple instances of the GPGPU1430are located in separate data processing systems and communicate via a network device that is accessible via the host interface1432. In one embodiment the GPU link1440can be configured to enable a connection to a host processor in addition to or as an alternative to the host interface1432.

While the illustrated configuration of the GPGPU1430can be configured to train neural networks, one embodiment provides alternate configuration of the GPGPU1430that can be configured for deployment within a high performance or low power inferencing platform. In an inferencing configuration the GPGPU1430includes fewer of the compute clusters1436A-1436H relative to the training configuration. Additionally, the memory technology associated with the memory1434A-1434B may differ between inferencing and training configurations, with higher bandwidth memory technologies devoted to training configurations. In one embodiment the inferencing configuration of the GPGPU1430can support inferencing specific instructions. For example, an inferencing configuration can provide support for one or more 8-bit integer dot product instructions, which are commonly used during inferencing operations for deployed neural networks.

Anti-Cheating Solution to Detect Graphics Driver Tampering

As described above, some online gaming players have developed hacking techniques to modify the graphics driver responsible for rendering graphics for the game to ignore depth information and draw all objects on the screen. These techniques are sometimes referred to as a “wallhack” because they enable players to see objects that are behind walls or other objects, lending the player an unfair advantage in the game. In some aspects, subject matter described herein addresses these and other issues by providing techniques to detect when a user has tampered with a graphics driver to change the output of the graphics driver in a manner that enables a user to view objects which should be hidden by walls or other obstacles.

FIG. 15illustrates a data processing system which may be adapted to implement an anti-cheating solution to detect graphics driver tampering, according to embodiments described herein. Referring toFIG. 15, in some examples a data processing system1500may be implemented as a heterogeneous processing system having a central processing unit (CPU) complex1510, a unified memory1530, and a general-purpose graphics processing unit (GPGPU)1540. The CPU complex1510comprises a1512which executes an operating system1514. One or more gaming applications1516may execute on the processor1512. CPU complex1510may further comprise a graphics device drive1520which, in turn, may comprise a user mode driver1522that executes a dispatcher1524. The processor can be implemented as any of the processors as described herein.

The GPGPU1540includes multiple compute blocks1544A-1544N, which include one or more instances of execution logic described herein. The GPGPU1540also includes a set of registers1545, cache memory1547, and a power and performance module1546that can be used as shared resources for the compute blocks1544A-1544N. In one embodiment the registers1545include directly and indirectly accessible registers, where the indirectly accessible registers may be optimized for use in matrix compute operations. The power and performance module1546can be configured to adjust power delivery and clock frequencies for the compute blocks1544A-1544N to power gate idle components within the compute blocks1544A-1544N under heavy workloads. The GPGPU1540includes GPGPU local memory1548, which are physical memory modules that share a graphics card or multi-chip module with the GPGPU1540.

The unified memory1530represents a unified address space that may be accessed by the processor1512and the GPGPU1540. The unified memory includes system memory1532as well as GPGPU memory1538. In some embodiments the GPGPU memory1538includes GPGPU local memory1534within the GPGPU1540and can also include some or all of system memory1532. For example, compiled code1534B stored in system memory1512can also be mapped into GPGPU memory1538for access by the GPGPU1540. In one embodiment a runtime library1536in system memory1532can facilitate the compilation and/or execution of compiled code1534B. The processor1512can execute instructions for a compiler1535stored in system memory1532. The compiler1535can compile source code1534A into compiled code1534B for execution by the processor1512and/or GPGPU1540. In one embodiment, the compiler1535is, or can include a shader compiler to compiler shader programs specifically for execution by the GPGPU1540.

In the example depicted inFIG. 15, a cheating detection module1518may be executed by one or both of the CPU complex1510or the GPGPU1540. In some examples the cheating detection module1518may be implemented as logic instructions embodied on a non-transitory computer-readable medium (i.e., software), while in other embodiment the cheating detection module1518may be reduce to firmware, logic circuitry, or combinations thereof.

FIG. 16illustrates aspects of a data processing environment1600may be adapted to implement an anti-cheating solution to detect graphics driver tampering, according to embodiments described herein. Referring toFIG. 16, in some examples the environment1600may comprise a gaming/anti-cheating server1610which hosts one or more online games. In some examples gaming server1610allows players to log into a game, synchronize, and to obtain the most recent information about opponents at different stages of the game. In some examples the gaming/anti-cheating server1610also implements operations to facilitate detecting cheating in online games by tampering with the graphics driver output. In some examples the gaming/anti-cheating server1610may be a single, unified server, while in other examples the gaming/anti-cheating server1610may be implemented by separate computing devices.

Gaming/anti-cheating server1610is communicatively coupled to a client system1620, which may be implemented in accordance with the description of a data processing device illustrated inFIG. 15. Client system1620may comprise a software guard extension (SGX) enclave1622which provides a trusted execution environment for operations in the client system1620. A gaming application1630executes on the client system. Client system1620further comprises an anti-cheating driver1640.

Having described various structural components to implement coarse compute shading, operations to implement coarse compute shading will be described with reference toFIGS. 17-18. In some examples the operations depicted inFIGS. 17-18may be implemented by the cheating detection module1518, alone or in combination with other components of a client system1600depicted inFIG. 16.

By way of overview, in one example the gaming/anti-cheating server1610inserts a random watermark in a random frame and sends the frame to the gaming application1630. In some examples the watermark may be inserted into a frame during a level change such that there is no impact on the user experience. The random watermark comprises an imaginer player or other object that is hidden behind an obstacle in the scene. The gaming/anti-cheating server1610sends a message which includes the colors of one or more random pixels in the watermark to the SGX enclave1622. In some examples the message may be encrypted with a shared secret. The SGX enclave1622renders the display frame with the help of the anti-cheating driver1640and compares the color of random pixels with the one received from the gaming/anti-cheating server1610. If there is a discrepancy between the color values, the SGX enclave1622will inform the gaming/anti-cheating sever1610for the further investigation.

In some examples the gaming/anti-cheating server1610and the SGX enclave1622implement a attestation process to establish a secure communication channel. This may be performed at any time, e.g., during a registration process. Attestation provides assurance to the gaming/anti-cheating server1610that the SGX enclave1622is a trustworthy partner with which to establish a secure communication channel. The secure communication channel ensures that all the communication between the gaming/anti-cheating server1610and the SGX enclave1622are encrypted with a shared secret exchanged during attestation and are immune to the man-in-middle attack. In some examples the shared secret for this communication may be mapped to the player and platform in the gaming/anti-cheating server1610as only this player and platform would be able to decrypt the information sent from the gaming/anti-cheating server1610.

To mitigate a man-in-the-middle attack between anti-cheating driver1640and the SGX enclave1622, during installation a secure encrypted channel is established between anti-cheating driver1640and the SGX enclave1622. In some examples there is a tamper resistant SW private key in anti-cheating driver1640and hardcoded public key in anti-cheating enclave. Further, the anti-cheating driver1640private key may be stored in a trusted platform module (TPM) register, while its public key is hardcoded in anti-cheating driver1640.

Operations in the attestation process are illustrated inFIG. 17. Referring toFIG. 17, at operation1710the SGX enclave1622generates an RSA Key Pair for the player/device, and at operation1725the SGX enclave1622sends a message to the gaming/anti-cheating server1610which contains SGX enclave quotes and the player/device public key. At operation1730the gaming server verifies the quote with the help of an attestation server and maps the player/device public key with the player/device.

At operation1735the gaming server encrypts the shared secret with the player/device public key, and at operation1740the SGX enclave1622decrypts and stores the shared secret in a computer readable memory such as a memory in the SGX enclave1622.

Once a secure communication channel is established between the SGX enclave1622and the gaming server, operations to detect graphics driver tampering may be implemented over the secure connection. Operations to implement this process are illustrated inFIG. 18. Referring toFIG. 18, at operation1810the gaming/anti-cheating server1610inserts one or more watermarks in one or more frames of the game. In some examples the watermark may be inserted into random frames and may comprise a player or other object in a scene that is hidden behind a wall or other object, such that the watermark should not be visible in the scene. The watermark(s) may be inserted during a level change such that user experience is not impacted. The frame including the watermark(s) are sent from the gaming server1610to the gaming application1630.

At operation1815the gaming/anti-cheating server1610encrypts a pixel data set comprising a frame identifier and pixel data for one or more pixels in the watermark and sends the encrypted pixel data to the SGX enclave1622, along with a time stamp for the watermark frame. In some examples the pixels in the pixel data may be selected randomly from the pixels comprised in the watermark that was inserted into the frame in operation1810. The pixel data may comprise location data and color data for the pixels selected to be in the pixel data set.

At operation1820the SGX enclave1622decrypts and stores the pixel data set received from the gaming/anti-cheating server1610, and at operation1825the SGX enclave1622sends a request to the anti-cheating driver1640to render the frame that includes the watermark inserted in operation1810at the time corresponding to the timestamp received from the gaming/anti-cheating server1610.

At operation1830the anti-cheating driver1640reads and signs the display buffer and at operation1835the anti-cheating driver1640sends the contents of the display buffer back to the SGX enclave1622.

At operation1840the SGX enclave1622verifies the signature of the frame buffer to ensure it is authenticated by and originated from the anti-cheating driver1640. At operation1845the SGX enclave1622determines whether the pixel data for the pixels received in the frame buffer from the anti-cheating driver1640are within a tolerated threshold range of the pixel data set extracted from the corresponding frame in operation1815. In some example the SGX enclave1622first locates the pixels in the frame buffer received from the anti-cheating driver1640which have a location that matches the location of the pixels in the data set generated in operation1815. The SGX enclave1622compares the color values of the pixels in the data set generated in operation1815with the color values of the pixels in the frame buffer received from the SGX enclave1622to determine whether the difference between the color values is within a predetermined threshold value.

In some examples the predetermined threshold value may be implemented as a constant value. In other examples the predetermined threshold value may be adjusted dynamically in response to a change in an operating condition of the gaming system. For example, the threshold value may be reduced in response to a determination that a player is playing at a level that exceeds the player's historical playing ability. Similarly, the threshold value may be reduced in response to a report from another player which suggests that the player may be cheating.

If, at operation1845, the differences between the pixel data for the selected pixels are below the threshold value then the game continues normally. By contrast, if at operation1845the difference between the pixel data for the selected pixels is above the threshold value then the SGX enclave1622sends a message to notify the gaming/anti-cheating server1610that there is a discrepancy between the pixel data extracted from the watermark in operation1815and the pixel data from the corresponding location of the frame buffer received in operation1835, which suggests that the output of the frame buffer has been altered.

With this information, the gaming/anti-cheating server1610can investigate the player and address the issue. For example, the gaming/anti-cheating server1610may inform the player that cheating is suspected. Alternatively, or in addition, the gaming/anti-cheating server1610may send a message to the SGX enclave1622requesting that the threshold value used in the comparison in operation1845be reduced. Alternatively, or in addition, the player may be evicted from the game.

FIG. 19is a block diagram of a computing device1900including a graphics processor1904, according to an embodiment. The computing device1900can be a computing device as described herein, such as the data processing system100as in ofFIG. 1. The computing device1900may also be or be included within a communication device such as a set-top box (e.g., Internet-based cable television set-top boxes, etc.), global positioning system (GPS)-based devices, etc. The computing device1900may also be or be included within mobile computing devices such as cellular phones, smartphones, personal digital assistants (PDAs), tablet computers, laptop computers, e-readers, smart televisions, television platforms, wearable devices (e.g., glasses, watches, bracelets, smartcards, jewelry, clothing items, etc.), media players, etc. For example, in one embodiment, the computing device1900includes a mobile computing device employing an integrated circuit (“IC”), such as system on a chip (“SoC” or “SOC”), integrating various hardware and/or software components of computing device1900on a single chip.

The computing device1900includes a graphics processor1904. The graphics processor1904represents any graphics processor described herein. The graphics processor includes one or more graphics engine(s), graphics processor cores, and other graphics execution resources as described herein. Such graphics execution resources can be presented in the forms including but not limited to execution units, shader engines, fragment processors, vertex processors, streaming multiprocessors, graphics processor clusters, or any collection of computing resources suitable for the processing of graphics and image resources.

In one embodiment the graphics processor1904includes a cache1914, which can be a single cache or divided into multiple segments of cache memory, including but not limited to any number of L1, L2, L3, or L4 caches, render caches, depth caches, sampler caches, and/or shader unit caches. In one embodiment, the graphics processor1904includes a scheduler1924, which can be a variant of the scheduler unit1622ofFIG. 16, or other scheduler logic described herein. The graphics processor1904can additionally include a command streamer1926, a thread dispatcher1934, and barrier/synchronization logic1936, in addition to a GPGPU engine1944that includes hardware logic to perform graphics processing and general-purpose instruction execution as described herein.

As illustrated, in one embodiment, and in addition to the graphics processor1904, the computing device1900may further include any number and type of hardware components and/or software components, including, but not limited to an application processor1906, memory1908, and input/output (I/O) sources1910. The application processor1906can interact with a hardware graphics pipeline, as illustrated with reference toFIG. 3, to share graphics pipeline functionality. Processed data is stored in a buffer in the hardware graphics pipeline and state information is stored in memory1908. The resulting data can be transferred to a display controller for output via a display device, such as the display device323ofFIG. 3. The display device may be of various types, such as Cathode Ray Tube (CRT), Thin Film Transistor (TFT), Liquid Crystal Display (LCD), Organic Light Emitting Diode (OLED) array, etc., and may be configured to display information to a user via a graphical user interface.

The application processor1906can include one or processors, such as processor(s)102ofFIG. 1and may be the central processing unit (CPU) that is used at least in part to execute an operating system (OS)1902for the computing device1900. The OS1902can serve as an interface between hardware and/or physical resources of the computer device1900and one or more users. The OS1902can include graphics driver logic1922, such as the user mode graphics driver1026and/or kernel mode graphics driver1029ofFIG. 10.

It is contemplated that in some embodiments the graphics processor1904may exist as part of the application processor1906(such as part of a physical CPU package) in which case, at least a portion of the memory1908may be shared by the application processor1906and graphics processor1904, although at least a portion of the memory1908may be exclusive to the graphics processor1904, or the graphics processor1904may have a separate store of memory. The memory1908may comprise a pre-allocated region of a buffer (e.g., framebuffer); however, it should be understood by one of ordinary skill in the art that the embodiments are not so limited, and that any memory accessible to the lower graphics pipeline may be used. The memory1908may include various forms of random access memory (RAM) (e.g., SDRAM, SRAM, etc.) comprising an application that makes use of the graphics processor1904to render a desktop or 3D graphics scene. A memory controller can be used to access data in the memory1908and forward the data to the graphics processor1904for graphics pipeline processing. The memory1908may be made available to other components within the computing device1900. For example, any data (e.g., input graphics data) received from various I/O sources1910of the computing device1900can be temporarily queued into memory1908prior to their being operated upon by one or more processor(s) (e.g., application processor1906) in the implementation of a software program or application. Similarly, data that a software program determines should be sent from the computing device1900to an outside entity through one of the computing system interfaces, or stored into an internal storage element, is often temporarily queued in memory1908prior to its being transmitted or stored.

The I/O sources can include devices such as touchscreens, touch panels, touch pads, virtual or regular keyboards, virtual or regular mice, ports, connectors, network devices, or the like. Additionally, the I/O sources1910may include one or more I/O devices that are implemented for transferring data to and/or from the computing device1900(e.g., a networking adapter); or, for a large-scale non-volatile storage within the computing device1900(e.g., hard disk drive). User input devices, including alphanumeric and other keys, may be used to communicate information and command selections to graphics processor1904. Another type of user input device is cursor control, such as a mouse, a trackball, a touchscreen, a touchpad, or cursor direction keys to communicate direction information and command selections to GPU and to control cursor movement on the display device. Camera and microphone arrays of the computer device1900may be employed to observe gestures, record audio and video and to receive and transmit visual and audio commands.

I/O sources1910configured as network interfaces can provide access to a network, such as a LAN, a wide area network (WAN), a metropolitan area network (MAN), a personal area network (PAN), Bluetooth, a cloud network, a cellular or mobile network (e.g., 3rdGeneration (3G), 4thGeneration (4G), etc.), an intranet, the Internet, etc. Network interface(s) may include, for example, a wireless network interface having one or more antenna(e). Network interface(s) may also include, for example, a wired network interface to communicate with remote devices via network cable, which may be, for example, an Ethernet cable, a coaxial cable, a fiber optic cable, a serial cable, or a parallel cable.

Network interface(s) may provide access to a LAN, for example, by conforming to IEEE 802.11 standards, and/or the wireless network interface may provide access to a personal area network, for example, by conforming to Bluetooth standards. Other wireless network interfaces and/or protocols, including previous and subsequent versions of the standards, may also be supported. In addition to, or instead of, communication via the wireless LAN standards, network interface(s) may provide wireless communication using, for example, Time Division, Multiple Access (TDMA) protocols, Global Systems for Mobile Communications (GSM) protocols, Code Division, Multiple Access (CDMA) protocols, and/or any other type of wireless communications protocols.

It is to be appreciated that a lesser or more equipped system than the example described above may be preferred for certain implementations. Therefore, the configuration of the computing device1900may vary from implementation to implementation depending upon numerous factors, such as price constraints, performance requirements, technological improvements, or other circumstances. Examples include (without limitation) a mobile device, a personal digital assistant, a mobile computing device, a smartphone, a cellular telephone, a handset, a one-way pager, a two-way pager, a messaging device, a computer, a personal computer (PC), a desktop computer, a laptop computer, a notebook computer, a handheld computer, a tablet computer, a server, a server array or server farm, a web server, a network server, an Internet server, a work station, a mini-computer, a main frame computer, a supercomputer, a network appliance, a web appliance, a distributed computing system, multiprocessor systems, processor-based systems, consumer electronics, programmable consumer electronics, television, digital television, set top box, wireless access point, base station, subscriber station, mobile subscriber center, radio network controller, router, hub, gateway, bridge, switch, machine, or combinations thereof.

The following clauses and/or examples pertain to specific embodiments or examples thereof. Specifics in the examples may be used anywhere in one or more embodiments. The various features of the different embodiments or examples may be variously combined with some features included and others excluded to suit a variety of different applications. Examples may include subject matter such as a method, means for performing acts of the method, at least one machine-readable medium including instructions that, when performed by a machine cause the machine to perform acts of the method, or of an apparatus or system according to embodiments and examples described herein. Various components can be a means for performing the operations or functions described.

Example 1 is an apparatus, comprising a processor to receive, from a gaming/anti-cheating server, a message comprising a first pixel data set comprising first pixel data for one or more pixels of a watermark generated by the gaming/anti-cheating server; store the first pixel data set in a machine-readable memory; receive, from a gaming system, a frame buffer rendered by the gaming system and comprising the watermark generated by the gaming/anti-cheating server; isolate, from the frame buffer, a second pixel data set comprising second pixel data for one or more pixels corresponding to the first pixel set; and forward an alert to the gaming/anti-cheating server when the second pixel data differs from the first pixel data by an amount that exceeds a threshold.

Example 2 may comprise the subject matter of example 1, the processor to establish a secure communication channel with the gaming/anti-cheating server.

Example 3 may comprise the subject matter of any one of examples 1-2, the processor to exchange a shared secret with the gaming/anti-cheating server during an attestation process, wherein the shared secret uniquely identifies a player and a platform; and use the shared secret to decrypt the first pixel data set.

Example 4 may comprise the subject matter of any one of examples 1-3, the processor to transmit, in response to receiving the first pixel data set, a frame buffer request to the gaming system.

Example 5 may comprise the subject matter of any one of examples 1-4, the processor to compare a first color value of the first pixel data set with a second color value of the second pixel data set; and forward an alert when a difference between the first color value of the first pixel data set and the second color value of the second pixel data set exceeds a threshold.

Example 6 may comprise the subject matter of any one of examples 1-5, wherein the threshold is a fixed value.

Example 7 may comprise the subject matter of any one of examples 1-6, the processor to adjust the threshold dynamically in response to a change in an operating condition of the gaming system.

Example 8 is a non-transitory machine readable medium storing instructions which, when executed by one or more processors, cause the one or more processors to receive, from a gaming/anti-cheating server, a message comprising a first pixel data set comprising first pixel data for one or more pixels of a watermark generated by the gaming/anti-cheating server; store the first pixel data set in a machine-readable memory; receive, from a gaming system, a frame buffer rendered by the gaming system and comprising the watermark generated by the gaming/anti-cheating server; isolate, from the frame buffer, a second pixel data set comprising second pixel data for one or more pixels corresponding to the first pixel set; and forward an alert to the gaming/anti-cheating server when the second pixel data differs from the first pixel data by an amount that exceeds a threshold.

Example 9 may comprise the subject matter of example 8, further comprising instructions which configure the processor to establish a secure communication channel with the gaming/anti-cheating server.

Example 10 may comprise the subject matter of any one of examples 8-9, further comprising instructions which configure the processor to exchange a shared secret with the gaming/anti-cheating server during an attestation process, wherein the shared secret uniquely identifies a player and a platform; and use the shared secret to decrypt the first pixel data set.

Example 11 may comprise the subject matter of any one of examples 8-10, further comprising instructions which configure the processor to transmit, in response to receiving the first pixel data set, a frame buffer request to the gaming system.

Example 12 may comprise the subject matter of any one of examples 8-11, further comprising instructions which configure the processor to compare a first color value of the first pixel data set with a second color value of the second pixel data set; and forward an alert when a difference between the first color value of the first pixel data set and the second color value of the second pixel data set exceeds a threshold.

Example 13 may comprise the subject matter of any one of examples 8-12, wherein the threshold is a fixed value.

Example 14 may comprise the subject matter of any one of examples 8-13, further comprising instructions which configure the processor to adjust the threshold dynamically in response to a change in an operating condition of the gaming system.

Example 15 is a computer-implemented method, comprising receiving, from a gaming/anti-cheating server, a message comprising a first pixel data set comprising first pixel data for one or more pixels of a watermark generated by the gaming/anti-cheating server; store the first pixel data set in a machine-readable memory; receiving, from a gaming system, a frame buffer rendered by the gaming system and comprising the watermark generated by the gaming/anti-cheating server; isolating, from the frame buffer, a second pixel data set comprising second pixel data for one or more pixels corresponding to the first pixel set; and forwarding an alert to the gaming/anti-cheating server when the second pixel data differs from the first pixel data by an amount that exceeds a threshold.

Example 16 may comprise the subject matter of example 15, further comprising establishing a secure communication channel with the gaming/anti-cheating server.

Example 17 may comprise the subject matter of any one of examples 15-16, further comprising exchanging a shared secret with the gaming/anti-cheating server during an attestation process, wherein the shared secret uniquely identifies a player and a platform; and using the shared secret to decrypt the first pixel data set.

Example 18 may comprise the subject matter of any one of examples 15-17, further comprising transmitting, in response to receiving the first pixel data set, a frame buffer request to the gaming system.

Example 19 may comprise the subject matter of any one of examples 15-18, further comprising comparing a first color value of the first pixel data set with a second color value of the second pixel data set; and forwarding an alert when a difference between the first color value of the first pixel data set and the second color value of the second pixel data set exceeds a threshold.

Example 20 may comprise the subject matter of any one of examples 15-19, wherein the threshold is a fixed value.

Example 21 may comprise the subject matter of any one of examples 15-20, further comprising adjusting the threshold dynamically in response to a change in an operating condition of the gaming system.

Embodiments may be provided, for example, as a computer program product which may include one or more machine-readable media having stored thereon machine-executable instructions that, when executed by one or more machines such as a computer, network of computers, or other electronic devices, may result in the one or more machines carrying out operations in accordance with embodiments described herein. A machine-readable medium may include, but is not limited to, floppy diskettes, optical disks, CD-ROMs (Compact Disc-Read Only Memories), and magneto-optical disks, ROMs, RAMs, EPROMs (Erasable Programmable Read Only Memories), EEPROMs (Electrically Erasable Programmable Read Only Memories), magnetic or optical cards, flash memory, or other type of media/machine-readable medium suitable for storing machine-executable instructions.

Moreover, embodiments may be downloaded as a computer program product, wherein the program may be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by way of one or more data signals embodied in and/or modulated by a carrier wave or other propagation medium via a communication link (e.g., a modem and/or network connection).

Those skilled in the art will appreciate from the foregoing description that the broad techniques of the embodiments can be implemented in a variety of forms. Therefore, while the embodiments have been described in connection with particular examples thereof, the true scope of the embodiments should not be so limited since other modifications will become apparent to the skilled practitioner upon a study of the drawings, specification, and following claims.